1. Field of the Invention
The invention relates to microphones, and more particularly to biasing circuits of microphones.
2. Description of the Related Art
Referring to FIG. 1A, a block diagram of a conventional microphone circuit 100 is shown. The conventional microphone circuit 100 comprises a microphone 102, a biasing circuit 104, and an integrated circuit 110. The microphone 102 is an electret condenser microphone (ECM) and comprises a transducer 112, a capacitor 114, and a transistor 116. When a sound pressure propagates to a diaphragm of the microphone 100, the diaphragm vibrates with the sound pressure, and a distance between the diaphragm and a back plate of the microphone 100 changes with the sound pressure. The diaphragm and the back plate forms the capacitor 114 with a capacitance changing with the distance between the back plate and the diaphragm, thereby converting the sound pressure to a voltage signal as an output of the microphone 102 at a node 152.
Because the microphone 102 requires external driving power to drive its operation, the biasing circuit 104 provides the microphone with a voltage source VA. The biasing circuit 104 comprises a resistor 122 and a capacitor 124. The resistor 122 is coupled between the voltage source VA and the node 152. The resistance of the resistor 122 ranges between 2.2 kΩ and 3.3 kΩ. The capacitor 124 isolates a DC bias voltage at the node 152 from a DC bias voltage at the node 154, passing only the AC portion of the voltage signal to the node 154.
The transistor 116 and the resistor 122 forms a first gain stage amplifying the voltage signal at the gate of the transistor 116 to obtain a voltage signal at the node 152. The voltage gain G1 of the first gain stage is determined according to the following algorithm:G1=gm×(R122∥R132);  (1)
wherein gm is the transconductance between the gate and the drain of the transistor 116, R122 is the resistance of the resistor 122, and R132 is the resistance of a resistor 132. An ordinary value of the voltage gain G1 is 1.
The integrated circuit 110 comprises a pre-amplifier circuit 106 and an analog-to-digital converter 108. The pre-amplifier circuit 106 comprises two resistors 132 and 134 and an operational amplifier 136. The pre-amplifier 106 forms a second gain stage amplifying the voltage signal at the node 154 to obtain a voltage signal at the node 156. The input resistor 132 is coupled between the node 154 and a negative input terminal of the operational amplifier 136. The feedback resistor 134 is coupled between the negative input terminal and an output terminal of the operational amplifier 136. The positive input terminal of the operational amplifier 136 is coupled to a voltage source VB. The gain G2 of the pre-amplifier circuit 106 is determined according to the following algorithm:
                                          G            2                    =                                    R                              f                ⁢                                                                  ⁢                b                                                    R                              i                ⁢                                                                  ⁢                n                                                    ;                            (        2        )            
wherein Rfb is the resistance of the feedback resistor 134, and Rin is the resistance of the input resistor 132. The analog-to-digital converter 108 then converts the amplified voltage signal at node 156 from analog to digital for further digital processing.
The input resistor 132 and the capacitor 124 forms a high pass filter. Referring to FIG. 1B, a Bode plot of the high pass filter comprising the capacitor 124 and the resistor 132 is shown. The cutoff frequency F3dB of the high pass filter is determined according to the following algorithm:
                                          F                          3              ⁢                                                          ⁢              dB                                =                      1                          2              ⁢                                                          ⁢              π              ×                              R                132                            ×                              C                124                                                    ;                            (        3        )            
wherein R132 is the resistance of the resistor 132, and C124 is the capacitance of the capacitor 124. Because human ears can hear sound with frequencies higher than 20 Hz, the cutoff frequency F3dB must be greater than 20 Hz to prevent a filtered signal from improper signal attenuation.
An ordinary resistance R132 of the input resistor 132 ranges from 10 kΩ to 50 kΩ. To keep the cutoff frequency F3dB greater than 20 Hz, the capacitance C124 of the capacitor 124 must therefore be greater than 0.1 μF according to the algorithm (3). Because a conventional semiconductor manufacturing process can only form a capacitor with a capacitance ranging from 1 fF to 100 pF in an integrated circuit, the capacitor 124 with a capacitance greater than 0.1 μF therefore cannot be merged into the integrated circuit 110. Thus, the biasing circuit 104 is formed on a printed circuit board and occupies a large layout space. Because portable devices such as cell phones have limited sizes to accommodate circuit components thereof, a microphone circuit 100 with a large layout space, however, cannot meet the size requirements of portable devices. Thus, a microphone circuit with a smaller size is required.